1. Field of the Invention
The present invention relates to an information processing technique, and particularly to an information processor that is provided with a memory having a hierarchical structure, and an information processing method applicable to the information processor.
2. Description of the Related Art
Due to the advancement of information processing techniques of recent years, a wide variety of functions can be easily implemented on an information processor by activating, for example, software recorded in CD-ROMs or other recording media or software downloaded from a network server. Under such circumstances, efficient and high-speed processing of programs has continued to be an important issue.
To enable high-speed processing, there needs to be not only an improvement in performance of processors but also an improvement in the data transfer rate between units in an information processor, such as between processor units or between a processor unit and a memory. One technique for enabling a processor's fast access to data or to a program stored in a memory is to hierarchize the memory using a cache memory. Generally, a cache memory has a capacity smaller than that of a main memory and enables fast data access. By storing frequently accessed data in a cache memory, the number of accesses to the main memory can be decreased, thereby reducing the overall time required for data access. Also, in a multiprocessor system comprising multiple processors, local memories provided in the respective processors enable fast access to a greater amount of data.
In order for a processor to process a program faster, the processor also needs to access the machine code faster. However, since a memory for enabling fast access, i.e., a high-speed memory, generally has a small capacity, programs often cannot be stored entirely therein, depending on the size of the program. In such case, a programmer needs to manually divide the program into multiple modules and also devise a way for loading such modules from the main memory into the high-speed memory at appropriate times.